Asic Chip Design for Heart Rate Monitoring and Signal Processing
DOI:
https://doi.org/10.53555/eee.v2i4.396Keywords:
Application Specific Integrated Circuit,, Heart rate variability (HRV),, Adaptive filter,, Electrocardiogram (ECG)Abstract
The objective of heart rate monitoring and processing devices is to perform automatic detection of cardiac arrhythmias in ECG signal. This work focuses on developing a sophisticated, small and reliable ASIC chip that can be used for monitoring and detecting the rate of heart beat for heart transplantation patient. Noise removal in heart rate signal is carried out by well known adaptive noise cancellation techniques such as LMS and RLS algorithms. In this work, ASIC chip is designed for heart rate monitoring and signal processing is done using LMS based adaptive algorithm. The proposed architectures have been modeled and verified for their functionality. Using the entire ASIC flow, suitable results obtained at various stages are compared and reported. The high computational requirement of all adaptive filtering algorithms has limited the scope of its use in medical applications. However, with rapid advances in VLSI technology, it is possible to implement complex circuits in a single chip. This work focuses on developing architectures for adaptive noise cancellation and its ASIC implementation.
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