FPGA Based Bl-CSC Converter-Fed Bldc Motor Drive with Power Factor Correction

Authors

  • K. Mohankumaramangalam PG Student, Department of EEE, Kathir College of Engineering, Coimbatore, India
  • B. Vaikundaselvan Professor & Head, Department of EEE, Kathir College of Engineering, Coimbatore, India
  • C. Sivan Raj Assisant Professor, Department of EEE, Kathir College of Engineering, Coimbatore, India

DOI:

https://doi.org/10.53555/eee.v3i6.378

Keywords:

BLDC Motor,, VSI, CSC, BL-CSC,, sensor-less,, diode bridge rectifier.

Abstract

This paper presents a Power Factor Correction (PFC) based Bridge Less Canonical Switching Cell (BL-CSC) converter-fed Brushless DC (BLDC) motor drive. The BL-CSC converter operating in a discontinuous inductor current mode is used to achieve a 0.99 power factor at the AC mains. The speed of the BLDC motor is controlled by varying the DC bus voltage using PI controller, where proportional and integral gains were tuned by conventional method. In order to reduce the switching losses of BLDC motor electronic commutation,Voltage Source Inverter (VSI) operates at fundamental frequency. Moreover, the bridgeless configuration of CSC converter offers low conduction losses due to partial elimination of diode bridge rectifier at the front end. The roposed configuration shows a considerable increase in efficiency.

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Published

2017-06-30

How to Cite

Mohankumaramangalam, K., Vaikundaselvan, B., & Sivan Raj, C. (2017). FPGA Based Bl-CSC Converter-Fed Bldc Motor Drive with Power Factor Correction. International Journal For Research In Electronics & Electrical Engineering, 3(6), 08–13. https://doi.org/10.53555/eee.v3i6.378

Issue

Vol. 3 No. 6 (2017): International Journal For Research In Electronics & Electrical Engineering

Section

Articles

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